The development of silicon-on-insulator (SOI) technology, in which devices are fabricated in a thin active layer of silicon overlying an insulator layer, has resulted in significant device performance improvements. Metal-oxide-semiconductor field effect transistors (MOSFET's) have been fabricated using SOI technology. Generally, MOSFET's operate by electronically varying the resistivity of a channel in a channel region, which is defined in the silicon active layer, along which carriers flow from a source to a drain, also defined in the silicon active layer and separated by a channel length. In n-channel MOSFET's, electrons are responsible for conduction in the channel and, in p-channel MOSFET's, holes are responsible for conduction in the channel. Output current is controlled by voltage applied to a polysilicon gate electrode, which is located above the channel region between the source and drain. The gate electrode is insulated from the channel region by a thin gate dielectric.
The material of the gate electrode is heavily doped polysilicon with a dopant concentration so that the gate electrode of the MOSFET is highly conductive. Similarly, portions of the silicon active layer are heavily doped with dopant concentrations effective to create the source and drain of the MOSFET. The source and drain are of the same conductivity type and are of opposite conductivity type to that of the channel region. N-channel MOSFET's are fabricated in a p-type portion of the active layer, normally with an n+-doped source and drain on opposite sides of an n+-doped polysilicon gate electrode and underlying p-type channel. P-channel MOSFET's are fabricated in an n-type portion of the active layer, normally with a p+-doped source and drain on opposite sides of a p+-doped polysilicon gate electrode and underlying n-type channel. Typically, n-wells defining n-type portions are formed by ion implantation or deposition and diffusion in a p-type active layer.
Ion implantation allows for exceptional control and reproducibility in the introduction of a dopant into thin surface layers, such as the silicon active layer and the gate electrode of MOSFET's. Implanted ions impinge the surface and travel below it to create, after the ions are fully stopped, a depth profile. In particular, controlling ion energy is one factor that establishes the depth profile of an implanted dopant. As a result, the semiconductor industry has accepted ion implantation as a preferred method for doping the gate electrode, source and drain of MOSFET's.
Downscaling to meet an increasing need for faster devices, higher performance, and lower power dissipation has driven the gate dielectric in MOSFET's to become ever thinner. As the gate dielectric thickness shrinks to less than two (2) nanometers, transistor performance has suffered because of the depletion of carriers in the polysilicon gate electrode when a voltage is applied to the gate electrode. Carrier depletion occurs when the device is fully turned on and free carriers are swept away from the base of the polysilicon gate electrode due to high vertical electric fields. Carrier depletion increases the effective thickness of the gate dielectric beyond its actual thickness, thereby reducing transistor performance. Carrier depletion may be alleviated by increasing the dopant concentration or doping level in the polysilicon gate electrode.
In one MOSFET fabrication scheme, the polysilicon gate electrode is doped simultaneously with the source and drain by a single ion implantation process. The energy of the implanted ions is selected such that their projected range in the active layer lies within the thickness of the active layer for forming the source and drain and their projected range in the gate electrode lies within the thickness of the gate electrode. For purposes of overcoming carrier depletion, however, merely increasing the implanted dose to elevate the dopant concentration in the polysilicon gate electrode sufficiently to overcome carrier depletion will increase the dopant concentration in the source and drain beyond design parameters. For example, increasing the implanted dose sufficient to produce a ten-fold increase in the dopant concentration in the gate electrode would increase the dopant concentration in the active layer by approximately an order of magnitude beyond design parameters.
In an alternative MOSFET fabrication scheme, a blanket layer of polysilicon is covered by a patterned photoresist layer and a gate dopant is implanted into unmasked areas of the pattern to create doped regions subsequently formed into gate electrodes. If the substrate is to carry both n-channel MOSFET's and p-channel MOSFET's, another mask and implant step is required to introduce a second dopant type for other gate electrodes. The gate electrode implantations are performed before gate electrode definition so that the high-dose implanted dopants do not penetrate into the source and drain, which are subsequently created by separate ion implantation or diffusion steps and with typical typical parameters. As a result, a critical etch step defining the gate electrodes must be done on polysilicon containing two different high concentrations of dissimilar dopant species, which significantly degrades linewidth control.
What is needed, therefore, is a method of ion implanting the source, the drain and the gate electrode of MOSFET's in a single process step performed without masking steps and without introducing excessive dopant concentrations into the source and drain.